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<p>MIPI DSI Tx Subsystem configuration structure.  
 <a href="struct_x_dsi_tx_ss___config.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:a61bc3ab2be7e74f0e2244e0c02295d4b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#a61bc3ab2be7e74f0e2244e0c02295d4b">DeviceId</a></td></tr>
<tr class="memdesc:a61bc3ab2be7e74f0e2244e0c02295d4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DeviceId is the unique ID of the device.  <a href="#a61bc3ab2be7e74f0e2244e0c02295d4b">More...</a><br/></td></tr>
<tr class="separator:a61bc3ab2be7e74f0e2244e0c02295d4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d585195086fad6ffb7623bbf1881d43"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#a7d585195086fad6ffb7623bbf1881d43">BaseAddr</a></td></tr>
<tr class="memdesc:a7d585195086fad6ffb7623bbf1881d43"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">    BaseAddress is the physical
</pre><p> base address of the subsystem address range  <a href="#a7d585195086fad6ffb7623bbf1881d43">More...</a><br/></td></tr>
<tr class="separator:a7d585195086fad6ffb7623bbf1881d43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad5bca47e3d8c2b12165513646ecb2a04"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#ad5bca47e3d8c2b12165513646ecb2a04">HighAddr</a></td></tr>
<tr class="memdesc:ad5bca47e3d8c2b12165513646ecb2a04"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">    HighAddress is the physical
</pre><p> MAX address of the subsystem address range  <a href="#ad5bca47e3d8c2b12165513646ecb2a04">More...</a><br/></td></tr>
<tr class="separator:ad5bca47e3d8c2b12165513646ecb2a04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a577c288549941ba5f8278307b62f1377"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#a577c288549941ba5f8278307b62f1377">DsiLanes</a></td></tr>
<tr class="memdesc:a577c288549941ba5f8278307b62f1377"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSI supported lanes 1, 2, 3, 4.  <a href="#a577c288549941ba5f8278307b62f1377">More...</a><br/></td></tr>
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<tr class="memitem:ae486561e1280ecbae8d0eed9899e897a"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#ae486561e1280ecbae8d0eed9899e897a">DataType</a></td></tr>
<tr class="memdesc:ae486561e1280ecbae8d0eed9899e897a"><td class="mdescLeft">&#160;</td><td class="mdescRight">RGB type.  <a href="#ae486561e1280ecbae8d0eed9899e897a">More...</a><br/></td></tr>
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<tr class="memitem:a5a11c849e71447b1fb262c771e62b705"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#a5a11c849e71447b1fb262c771e62b705">DsiByteFifo</a></td></tr>
<tr class="memdesc:a5a11c849e71447b1fb262c771e62b705"><td class="mdescLeft">&#160;</td><td class="mdescRight">128, 256, 512, 1024, 2048, 4096, 8192, 16384  <a href="#a5a11c849e71447b1fb262c771e62b705">More...</a><br/></td></tr>
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<tr class="memitem:aa0ed323752a5c083372f5c56e4c2aaea"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#aa0ed323752a5c083372f5c56e4c2aaea">CrcGen</a></td></tr>
<tr class="memdesc:aa0ed323752a5c083372f5c56e4c2aaea"><td class="mdescLeft">&#160;</td><td class="mdescRight">CRC Generation enable or not.  <a href="#aa0ed323752a5c083372f5c56e4c2aaea">More...</a><br/></td></tr>
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<tr class="memitem:a1e7abd1f22f0673c4620ac24c0bd75f4"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#a1e7abd1f22f0673c4620ac24c0bd75f4">DsiPixel</a></td></tr>
<tr class="memdesc:a1e7abd1f22f0673c4620ac24c0bd75f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pixels per beat received on input stream.  <a href="#a1e7abd1f22f0673c4620ac24c0bd75f4">More...</a><br/></td></tr>
<tr class="separator:a1e7abd1f22f0673c4620ac24c0bd75f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a51f7855b03e97c7106fed916fa842e72"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#a51f7855b03e97c7106fed916fa842e72">DphyLinerate</a></td></tr>
<tr class="memdesc:a51f7855b03e97c7106fed916fa842e72"><td class="mdescLeft">&#160;</td><td class="mdescRight">DPHY line rate.  <a href="#a51f7855b03e97c7106fed916fa842e72">More...</a><br/></td></tr>
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<tr class="memitem:aa773bef1fcc5616169b86d4a4d559eb8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#aa773bef1fcc5616169b86d4a4d559eb8">IsDphyRegIntfcPresent</a></td></tr>
<tr class="memdesc:aa773bef1fcc5616169b86d4a4d559eb8"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">Flag for DPHY register
</pre><p> interface presence  <a href="#aa773bef1fcc5616169b86d4a4d559eb8">More...</a><br/></td></tr>
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<tr class="memitem:a726206548f75b4e56967dfd6523b3485"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dsi_tx_ss_sub_core.html">DsiTxSsSubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#a726206548f75b4e56967dfd6523b3485">DphyInfo</a></td></tr>
<tr class="memdesc:a726206548f75b4e56967dfd6523b3485"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a726206548f75b4e56967dfd6523b3485">More...</a><br/></td></tr>
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<tr class="memitem:ae37e75593d8c004c2a745b25a503f9c4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dsi_tx_ss_sub_core.html">DsiTxSsSubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dsi_tx_ss___config.html#ae37e75593d8c004c2a745b25a503f9c4">DsiInfo</a></td></tr>
<tr class="memdesc:ae37e75593d8c004c2a745b25a503f9c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ae37e75593d8c004c2a745b25a503f9c4">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>MIPI DSI Tx Subsystem configuration structure. </p>
<p>Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a7d585195086fad6ffb7623bbf1881d43"></a>
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<p><pre class="fragment">    BaseAddress is the physical
</pre><p> base address of the subsystem address range </p>

<p>Referenced by <a class="el" href="xdsitxss__intr__example_8c.html#af332a23bd0cd610cf1e95df34b70c998">DsiTxSs_IntrExample()</a>, <a class="el" href="xdsitxss__selftest__example_8c.html#a45fd3120f2e09254f53e6181be47269c">DsiTxSs_SelfTestExample()</a>, <a class="el" href="xdsitxss__video__test__example_8c.html#a17e686b9a365a72175c35bd7be2566ac">DsiTxSs_VideoTestExample()</a>, and <a class="el" href="group__dsitxss.html#gaa4193394015188a834eeeee8e5da3e40">XDsiTxSs_CfgInitialize()</a>.</p>

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          <td class="memname">u8 XDsiTxSs_Config::CrcGen</td>
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<p>CRC Generation enable or not. </p>

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          <td class="memname">u8 XDsiTxSs_Config::DataType</td>
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<p>RGB type. </p>

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          <td class="memname">u32 XDsiTxSs_Config::DeviceId</td>
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<p>DeviceId is the unique ID of the device. </p>

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          <td class="memname"><a class="el" href="struct_dsi_tx_ss_sub_core.html">DsiTxSsSubCore</a> XDsiTxSs_Config::DphyInfo</td>
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<p>Sub-core instance configuration. </p>

<p>Referenced by <a class="el" href="group__dsitxss.html#gacdbf8bdffcc5c58bafabca09ce89ffbb">XDsiTxSs_ReportCoreInfo()</a>, and <a class="el" href="group__dsitxss.html#ga5c2a0c949b32000d56edf503bcee3b48">XDsiTxSs_SelfTest()</a>.</p>

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          <td class="memname">u32 XDsiTxSs_Config::DphyLinerate</td>
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<p>DPHY line rate. </p>

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<p>128, 256, 512, 1024, 2048, 4096, 8192, 16384 </p>

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          <td class="memname"><a class="el" href="struct_dsi_tx_ss_sub_core.html">DsiTxSsSubCore</a> XDsiTxSs_Config::DsiInfo</td>
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<p>Sub-core instance configuration. </p>

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          <td class="memname">u8 XDsiTxSs_Config::DsiLanes</td>
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<p>DSI supported lanes 1, 2, 3, 4. </p>

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<p>Pixels per beat received on input stream. </p>

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<p><pre class="fragment">    HighAddress is the physical
</pre><p> MAX address of the subsystem address range </p>

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<p><pre class="fragment">Flag for DPHY register
</pre><p> interface presence </p>

<p>Referenced by <a class="el" href="group__dsitxss.html#ga72465c9ad620c0103bfdc2055f4db426">XDsiTxSs_Reset()</a>.</p>

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